Combinational Circuits

Combinational circuit

Each output depends entirely on the immediate (present) inputs.

Sequential circuit

Each output depends on both present inputs and state

Analysis Procedure

1. Label inputs and outputs
2. Obtain the functions of intermediate points and the outputs
3. Draw the truth table
4. Deduce the functionality of circuit

Step 1: Label inputs and outputsABF1F2Step 2: Functions of intermediate pointsABF1F2A+BA'+B'Step 3: Truth Table000100011110101110111001Step 4: Deduce functionalityHalf-adder. # Design Methods

Combinational circuit design methods:

• Gate level design method (with logic gates)
• Block level design method (with functional blocks)

Design methods use logic gates and function blocks available as Integrated Circuit (IC) chips. Types of IC chips based on packing density: SSI, MSI, LSI, VLSI, ULSI.

Main objectives:

• Reduce cost (number of gates for small circuits, number of IC packages for complex circuits)
• Increase speed
• Design simplicity (block reuse)

Gate-level design

1. State problem
2. Determine label inputs and outputs of circuit
3. Draw truth table
4. Obtain simplified Boolean functions
5. Draw logic diagram

Step 1Build a half-adderProblem:Step 2Determining and labeling input/outputsHalf-AdderXYSC(X + Y)Step 3Truth tableXYCS0000010110011110Step 4Obtain simplified Boolean functionsStep 5Logic diagramABSC

Step 1Build a full-adderProblem:Step 2Determining and labeling input/outputsFull-AdderXYSC(X + Y + Z)Step 3Truth tableX0Step 4Obtain simplified Boolean functionsStep 5Logic diagramXYZ0001111Y00110011Z01010101S00010111C01101001ZSC

Block-Level Design

More complex circuits are built using block-level methods. We can use 4-bit parallel adders as building blocks, we can create the following:

1. BCD-to-Excess-3 Code Converter
2. 16-bit Parallel Adder

# Magnitude Comparator

Magnitude Comparator

Compares 2 unsigned values to check

A3A2A1A0B3B2B1B04-bitComp(A < B)(A > B)(A = B) # Circuit Delays

Circuit delay

Given a logic gate with delay , if inputs are stable at times , then the earliest time in which the output will be stable is: