There are 2 types of sequential circuits:

  • Synchronous: outputs change at specific time
  • Asynchronous: Changes at any time

Multivibrator

Class of sequential circuits

  • Bistable (2 stable states)
  • Monostable or one-shot (1 stable state)
  • Astable (no stable state)

Bistable logic devices

Latches, and flip flops.

Memory Elements

Memory element

A device which can remember value indefinitely, or change value on command from its inputs.

Memoryelementcommandstored valueQCommand at time (t)Q(t)Q(t+1)current statenext statesetX1resetX0memorise1100positive edgesnegative edgespositive pulsesclocksquare waveEdge-triggeredFlip-flopsPositive edge-triggered (ON on positive edges, OFF otherwise)10Negative edge-triggered (ON on negative edges, OFF otherwise)Pulse-triggeredLatchesON = 1, OFF = 0

Latch

S-R Latch

S-R Latch

Two inputs: S and R Two complementary outputs: Q and Q'

State Q = HIGH: SET Q' = LOW: RESET

LOW
initial
HIGH
HIGH
invalid
SRQQ'00NCNCNo change.1010Latch SET0101Latch RESET1100InvalidSRQQ'RSQQ'

Active-Low S-R Latch

NAND gates are used instead for this. For these latches, given the input SR:

  • 00 becomes an invalid command (no change in Active-High)
  • 11 becomes a nochange command (invalid in Active-High)
  • 01 becomes a set command (reset in Active-High)
  • 10 becomes a reset command (set in Active-High)

Gated S-R Latch

Gated S-R Latch

S-R latch + enable input (EN) and 2 NAND gates

SRENQQ'Outputs only change when EN is highStill possible for invalid state

Gated D Latch

DENQQ'set R = S'eliminates invalid conditionENDQ(t+1)1001110XQ(t)ResetSetNo Change With the gated `D` latch, the invalid condition is eliminated.

Flip-Flops

Synchronous bistable devices

Output changes state as a specified point on a triggering input called the clock:

SCRQQ'SCRQQ'Positive-edge triggeredNegative-edge triggeredS-R flip-flopDCQQ'DCQQ'Positive-edge triggeredNegative-edge triggeredD flip-flopJCQQ'JCQQ'Positive-edge triggeredNegative-edge triggeredJ-K flip flopKKhas invalid conditionsconvert S-R flip-flopinto a D flip-flop;add an inverterParallel data transferQ and Q' are fedback to pulse-steeringNAND gatesUse CaseToggle state when JK = 11

S-R flip flop

No change
Reset
Set
Invalid

D flip flop

Set
Reset

J-K flip flop

Pulse transitiondetectorJCLKKQQ'JCQQ'K
No change
Reset
Set
Toggle

T flip flop

Pulse transitiondetectorJCLKQQ'JCQQ'KTCLK
No change
Toggle

Asynchronous Inputs

The S-R, D, J-K inputs are synchronous inputs as data on these inputs are transferred to the flip-flop’s output only on the triggered edge of the clock pulse.

Asynchronous

Affect the state of the flip flop independent of the clock

PRE = HIGH: Q is immediately set to HIGH

CLR = HIGH: Q is immediately cleared to LOW

Flip-flop in normal operation mode when both PRE and CLR are LOW.

Synchronous Sequential Circuits

Note

Flip flops make up the memory while the gates form one or more combinational sub-circuits.

No change
Reset
Set
Invalid/Unpredictable
Set
Reset
No change
Reset
Set
Toggle
No change
Toggle

Analysis of Sequential Circuits

Analysing behaviour

  1. Derive state table
  2. and hence its state diagram

Requires state equations to be derived for the flip-flop inputs as well as output functions for the circuit outputs other than the flip-flops other than flip flops.

or and or can represent the present state and next state of a flip-flop represented by .

State table

Similar to a truth table. Inputs and present state on left side. Outputs and next state on the right side.

flip-flops and inputs rows

Present StateNext StateInputOutputABxAB++ym flip flopsn inputsrowsPresent StateNext StateA BA B++FULL TABLEAB++x=0x=1Outputyyx=0x=1COMPACT TABLE

State diagram

  • Each state is denoted by a circle
  • Each arrow denotes a transition of the sequential circuit
Present StateNext StateA BA B++AB++x=0x=1Outputyyx=0x=100000100010011101000101011001010001011010/01/00/11/00/11/00/11/0input/output

Circuit output functions

The outputs of a sequential circuit are functions of the present states of the flip-flops and the inputs. The algebraic description of these are the circuit output functions.

Flip-flop input functions/equations

Algebraic descriptions of the part of the circuit that generates inputs to the flip-flops.

This determines the next state generation - using the functions and the characteristic tables, the next states of flip-flops can be obtained.

Flip-flop Excitation Tables

Analysis

Starting from a circuit diagram, derive state table or state diagram

Characteristic tables

Design

Starting from a set of specifications (in the form of state equations, state table, state diagram), derive logic circuit.

Excitation tables

Excitation tables

Input: Required transition from present state to next state Output: Flip-flop inputs

QQ+00011011JK0X1XX1X0JK Flip-flopQQ+00011011SR0X1001X0SR Flip-flopQQ+00011011D0101D Flip-flopQQ+00011011T0110T Flip-flop

Design procedure:

  • Circuit specifications
    • Description of circuit behaviour - state diagram/state table
  • Derive state table
  • Perform state reduction if necessary
  • Perform state assignment
  • Determine number of flip-flops and label them
  • Choose type of flip-flop to be used
  • Derive circuit excitation and output tables from the state table
  • Derive circuit output functions and flip-flop input functions
  • Draw the logic diagram

Worked example:

0001101100000111111Given state diagram: > [!question] How many flip-flops are needed? > > Since two bits are needed to represent each state, two flip-flops are needed. > > The flip-flops can be allocated as `A` and `B`.

How many input variables are there?

The input variables are only 0 and 1, meaning there is one input variable.

The input variable can be allocated x.

Present State at at
000001
011001
101011
111100

Using JK Flip-flop excitation table

000X
011X
10X1
11X0

We can get the state table:

000000X0X
001010X1X
010101XX1
011010XX0
10010X00X
10111X01X
11011X0X0
11100X1X1
combinational circuitxKJQ'QKJQ'QCPA'ABB'KAJAKBJBAA'AB'B

X00X00X0X0X1XABxX0X0X1XABx0011XXXABxXXX11ABx KJQ'QKJQ'QABxCP # Sink State

Sink state

A state that never moved out of itself to other states