Registers

  1. $zero
  2. $at
  3. $v0
  4. $v1
  5. $a0
  6. $a1
  7. $a2
  8. $a3
  9. $t0
  10. $t1
  11. `$t2
  12. $t3
  13. $t4
  14. $t5
  15. $t6
  16. $t7
  17. $s0
  18. $s1
  19. $s2
  20. $s3
  21. $s4
  22. $s5
  23. $s6
  24. $s7
  25. $t8
  26. $t9
  27. `$k0
  28. $k1
  29. $gp
  30. $sp
  31. `$fp
  32. $ra

R-format

Opcode = 0x0

opcodersrdrtfunctshamt3126212516201115610056 bits5 bits5 bits5 bits5 bits6 bitsonly forshift functionssource registertarget registerdestination register000000if first 2 hex digits of instruction is < 0x04, instruction is of R-formatR-format

MnemonicOperationFunct(binary)
addR[rd] = R[rs] + R[rt]2010 0000
adduR[rd] = R[rs] + R[rt]2110 0001
andR[rd] = R[rs] & R[rt]2410 0100
jrPC = R[rs]0800 1000
norR[rd] = ~(R[rs] OR R[rt])2710 0111
orR[rd] = R[rs] OR R[rt]2510 0101
sltR[rd] = (R[rs] < R[rt]) ? 1 : 02a10 1010
sltuR[rd] = (R[rs] < R[rt]) ? 1 : 02b10 1011
sllR[rd] = R[rt] << shamt000 0000
sltR[rd] = R[rt] >> shamt200 0010
subR[rd] = R[rs] - R[rt]2210 0010
subuR[rd] = R[rs] - R[rt]2310 0011

I-format

opcodersimmediatert3126212516201506 bits5 bits5 bits16 bitssource registertarget registerif first 2 hex digits of instruction is > 0x04, instruction is of I-formatI-format

MnemonicOperationOpcode(binary)
addiR[rt] = R[rs] + SignExtImm0x0800 1000
addiuR[rt] = R[rs] + SignExtImm0x0900 1001
andiR[rt] = R[rs] & ZeroExtImm0x0c00 1100
beqif (R[rs] == R[rt]) PC = PC + 4 + BranchAddr0x0400 0100
bneif (R[rs] != R[rt]) PC = PC + 4 + BranchAddr0x0500 0101
luiR[rt] = {imm, 16'b0}0x0f00 1111
lwR[rt] = M[R[rs] + SignExtImm]0x2310 0011
oriR[rt] = R[rs] or ZeroExtImm0x0d00 1101
sltiR[rt] = (R[rs] < SignExtImm) ? 1 : 00x0a00 1010
sltiuR[rt] = (R[rs] < SignExtImm) ? 1 : 00x0b00 1011
swM[R[rs] + SignExtImm] = R[rt]0x2b10 1011
sbM[R[rs] + SignExtImm](7:0) - R[rt](7:0)0x2810 1000

J-format

opcodeaddress31262506 bits26 bitsR-format

MnemonicOperationOpcode(binary)
jPC = JumpAddr0x0200 0010